The present invention relates to motor controllers and more particularly, to a method and an apparatus for altering stator winding voltages to eliminate greater than twice over voltage.
Many motor applications require that a motor be driven at various speeds. Motor speed can be adjusted with an Adjustable Speed Drive (ASD) which is placed between a voltage source and an associated motor that can excite the motor at various frequencies. One commonly used type of ASD uses a three-phase Pulse Width Modulated (PWM) inverter and associated PWM controller which can control both voltage and frequency of signals that eventually reach motor stator windings.
A three-phase PWM controller receives three reference or modulating signals and a triangle carrier signal, compares each modulating signal to the carrier signal and generates firing signals consisting of a plurality of pulses corresponding to each modulating signal. When a modulating signal has a greater instantaneous amplitude than the carrier signal, a corresponding firing signal is high producing a pulse on-time. When a modulating signal has an instantaneous amplitude that is less than the carrier signal, a corresponding firing signal is low producing a pulse off-time.
The firing signals are used to control the PWM inverter. A three-phase PWM inverter consists of three pairs of switches, each switch pair including series arranged upper and lower switches configured between positive and negative DC power supplies. Each pair of switches is linked to a unique motor terminal by a unique supply line, each supply line is connected to a node between an associated pair of switches. Each firing signal controls an associated switch pair to alternately connect a stator winding between the positive and negative DC power supplies to produce a series of high frequency voltage pulses that resemble the firing signals. A changing average of the high frequency voltage pulses over a period defines a fundamental low frequency alternating line-to-line voltage between motor terminals that drives the motor.
Insulated Gate Bipolar Transistors (IGBTs) are the latest power semiconductor switches used in the PWM inverter, IGBTs have fast rise times and associated switching speeds (e.g. 50-400 ns) that are at least an order of magnitude faster than BJTs and other similar devices. At IGBT switching speeds, switching frequency and efficiency, and the quality of terminal voltages, are all appreciably improved. In addition, the faster switching speeds reduce harmonic heating of the motor winding as well as reduce audible motor lamination noise.
While IGBT PWMs are advantageous for all of the reasons identified above, when combined with certain switch modulating techniques (i.e. certain on/off switching sequences), IGBT fast dv/dt or rise times can reduce the useful life of motor components and/or drive to motor voltage supply lines. In particular, while most motors and supply lines are designed to withstand operation at rated line voltages for long periods and to withstand predictable overvoltage levels for short periods, in many cases, fast switch rise times causes overvoltages that exceed design levels.
For a long time the industry has recognized and configured control systems to deal with twice overvoltage (i.e. twice the PWM inverter DC power supply level) problems. As well known in the controls art, twice overvoltage levels are caused by various combinations of line voltage rise time and magnitude, imperfect matches between line-to-line supply cable and motor surge impedances, and cable length. Line voltage frequency and switch modulating techniques have little effect on twice overvoltage levels.
One common way to cope with twice overvoltage levels has been to reduce reflected voltage by terminating the cable supply lines at the motor terminals with a cable to motor surge impedance matching network. Resistor-Inductor-Capacitor or R-L-C filter networks mounted at the drive output are also used to change and reduce the slope of the voltage pulses (i.e. the turn on times) as they arrive. This network increases the cable distance where twice voltage in the motor terminals is developed to a length outside the application distance of interest. In addition, to reduce the possibility of damage from periodic twice overvoltage levels, most cable supply lines and motors are insulated to withstand periodic twice overvoltage levels. Thus, the industry has developed different system configurations for dealing with twice overvoltage.
Unfortunately, there is another potentially more damaging overvoltage problem that has not been satisfactorily dealt with. The second overvoltage problem is referred to herein as greater than twice overvoltage. Unlike twice overvoltage, greater than twice overvoltage is caused by faster IGBT switching frequencies and faster IGBT dv/dt rise times interacting with two different common switch modulating techniques, that result in overvoltage problems referred to as "double pulsing" and "polarity reversal".
Referring to FIG. 1, double pulsing will be described in the context of an IGBT inverter generated line-to-line voltage V.sub.i applied to a line cable and a resulting motor line-to-line terminal voltage V.sub.m. Initially, at time .tau..sub.1, the line is shown in a fully-charged condition (V.sub.i (.tau..sub.1)=V.sub.m (.tau..sub.1)=V.sub.DC). A transient motor voltage disturbance is initiated in FIG. 1 by discharging the line at the inverter output to zero voltage, starting at time .tau..sub.2, for approximately 4 .mu.sec. The pulse propagation delay between the inverter terminals and motor terminals is proportional to cable length and is approximately 1 .mu.sec for the assumed conditions. At time .tau..sub.3, 1 .mu.sec after time .tau..sub.2, a negative going V.sub.DC voltage has propagated to the motor terminals. In this example, a motor terminal reflection coefficient .GAMMA..sub.m is nearly unity. Thus, the motor reflects the incoming negative voltage and forces the terminal voltage V.sub.m to approximately negative bus voltage: EQU V.sub.m (.tau..sub.3)=V.sub.m (.tau..sub.1)-V.sub.DC (1+.GAMMA..sub.m).apprxeq.-V.sub.DC Eq. 1
A reflected wave (-V.sub.DC) travels from the motor to the inverter in 1 .mu.sec and is immediately reflected back toward the motor. Where an inverter reflection coefficient .GAMMA..sub.i is approximately negative unity, a positive V.sub.DC pulse is reflected back toward the motor at time .tau..sub.4. Therefore, at time .tau..sub.4 the discharge at time .tau..sub.2 alone causes a voltage at the motor terminal such that: EQU V.sub.m (.tau..sub.4)=V.sub.m (.tau..sub.1)-V.sub.DC (1+.GAMMA..sub.m)-V.sub.DC .GAMMA..sub.i .GAMMA..sub.m (1+.GAMMA..sub.m).apprxeq.V.sub.DC Eq. 2
In addition, at time .tau..sub.4, with the motor potential approaching V.sub.DC due to the .tau..sub.2 discharge, the inverter pulse V.sub.i (.tau..sub.4) arrives and itself recharges the motor terminal voltage to V.sub.DC. Pulse V.sub.i (.tau..sub.4) is reflected by the motor and combines with V.sub.m (.tau..sub.4) to achieve a peak value of approximately three times the DC rail value: EQU V.sub.m (.tau..sub.4 +)=V.sub.m (.tau..sub.1)-V.sub.DC (1+.GAMMA..sub.m)-V.sub.DC .GAMMA..sub.i .GAMMA..sub.m (1+.GAMMA..sub.m)+V.sub.i (.tau..sub.4) (1+.GAMMA..sub.m).apprxeq.3V.sub.DCEq. 3
Referring to FIG. 2 polarity reversal will be described in the context of an IGBT inverter generated line-to-line voltage V.sub.il and a resulting motor line-to-line voltage V.sub.ml. Polarity reversal occurs when the firing signal of one supply line is transitioning into overmodulation while the firing signal of another supply line is simultaneously transitioning out of overmodulation. Overmodulation occurs when a reference signal magnitude is greater than the maximum carrier signal magnitude so that the on-time or off-time of a switch is equal to the duration of the carrier period. Polarity reversal is common in all types of PWM inverter control.
Initially, the inverter line-to-line voltage V.sub.i1 (.tau..sub.5) is zero volts. At time .tau..sub.6, the inverter voltage V.sub.il (.tau..sub.6) is increased to V.sub.DC and, after a short propagation period, a V.sub.DC pulse is received and reflected at the motor terminals thus generating a 2V.sub.DC pulse across associated motor lines. At time .tau..sub.7, the line-to-line voltage switches polarity (hence the term polarity reversal) so that the inverter voltage V.sub.i1 (.tau..sub.7) is equal to -V.sub.DC thus sending a -2V.sub.DC pulse to the motor when the line-to-line motor voltage V.sub.ml (.tau..sub.7) has not yet dampened out to a DC value (i.e. may in fact be 2V.sub.DC). After a short propagation period, the -2V.sub.DC pulse reaches the motor, reflects, and combines with the inverter reflected pulse -V.sub.DC, its reflected component and the positive voltage 2V.sub.DC on the motor. The combination generates an approximately -4V.sub.DC line-to-line motor voltage V.sub.ml (.tau..sub.8) at time .tau..sub.8.
In reality, the amplitude of overvoltages will often be less than described above due to a number of system variables including line AC resistance damping characteristics, DC power supply level, pulse dwell time, carrier frequency f.sub.c modulation techniques, and less than unity reflection coefficients (.GAMMA..sub.m).
One solution to the double pulsing problem has been to increase the zero voltage dwell time between line-to-line inverter pulses. In other words, referring again to FIG. 1, the discharge time between pulses would be extended from the present 4 .mu.secs so that, prior to the second pulse V.sub.i (.tau..sub.4) reaching the motor terminals, the motor terminal voltage transient V.sub.m reaches a steady state DC value.
While increasing the zero voltage dwell time between line-to-line inverter pulses eliminates greater than twice overvoltage due to double pulsing, this solution can disadvantageously reduce the amplitude of the resulting fundamental low frequency terminal voltage where high carrier frequencies and overmodulation occurs. For example, referring to FIG. 3, a series of high frequency voltage pulses 5 at a motor terminal and a resulting fundamental low frequency terminal voltage 6 can be observed. In FIG. 3, a positive phase of the low frequency voltage begins at .tau..sub.9 and ends at .tau..sub.10.
To eliminate greater than twice over voltage, one pulse limiting scheme indiscriminately increases the duration of each off time period that is less than a minimum allowable off time. In FIG. 3, off times of pulses during the over modulation period (i.e., .zeta..sub.2 and .zeta..sub.3) are less than the minimum allowable off time and therefore result in on times greater than the maximum on time and thus all would be limited. In addition, in many cases greater than twice over voltage will occur prior to and just after overmodulation. Thus, referring still to FIG. 3, during periods just before period .zeta..sub.2, and just after period .zeta..sub.3, off times will also often be limited. Where the magnitude of the DC power supply is reduced substantially, the number of overmodulation carrier periods having limited on-times increases proportionally until, at some point, the reduced on-time noticeably affects the low frequency terminal voltage magnitude. In other words, maximum power output is substantially reduced through blind limitation of firing pulses during overmodulation.
While FIG. 3 is only exemplary, it can be seen that during the positive phase (i.e. .tau..sub.9 -.tau..sub.10), the four firing pulses that would normally occur during carrier periods .zeta..sub.1 -.zeta..sub.4 would likely all be limited to a maximum on-time according to prior art methods of reducing greater than twice overvoltage. In addition, pulses during periods just before period .zeta..sub.1 and just after period .zeta..sub.4 may also be limited. In many cases, especially where the DC supply magnitude is minimal or reduced, the reduction in low frequency terminal voltage is unacceptable.
In addition to reducing the magnitude of the fundamental low frequency voltage 6, this solution does not address the polarity reversal problem.
Another solution to the greater than twice overvoltage problem is described in U.S. patent application Ser. No. 08/701,950 entitled METHOD AND APPARATUS FOR CONTROLLING VOLTAGE REFLECTIONS USING A MOTOR CONTROLLER which was filed on Aug. 23, 1996 and is commonly owned with this application. According to this solution a motor controller modifies firing pulses that are provided to an inverter in a manner calculated to eliminate greater than twice overvoltage switching sequences. When the period between two voltage changes is less than the period required for a substantially steady state voltage near zero to be reached, the period between the two changes is increased. Where overmodulation switching sequences result in greater than twice overvoltage due to polarity reversal, the overmodulation switching sequence is altered to eliminate the possibility of greater than twice overvoltage.
This solution contemplates two different methods of altering the switching sequence referred to as the Maximum-Minimum Pulse Technique (MMPT) and the Pulse Elimination Technique (PET) methods. According to the MMPT method, when a PWM pulse has characteristics which could generate greater than twice overvoltage, the pulse width is altered so that its duration is set equal to or between the minimum and maximum pulse times allowed. Importantly, only pulses that cross the threshold level for double pulsing induced motor voltages greater than twice overvoltage and during polarity reversal periods are altered so that the resulting terminal voltage magnitude is only minimally effected. Nevertheless, the terminal voltage magnitude is noticeably reduced as some positive pulse durations during positive half cycles and some negative pulse durations during negative half cycles are reduced when the MMPT method is employed.
According to the PET method, instead of only limiting pulses to within the maximum and minimum pulse times, some of the pulses having characteristics which could generate greater than twice overvoltage are eliminated. In other words, some of the positive pulse durations during positive half cycles are increased and set equal to the carrier period and some of the negative pulse durations are increased and set equal to the carrier period which tend to offset the reduced pulse durations. The result is a terminal voltage magnitude which is essentially unaffected by pulse alterations.
While this solution effectively eliminates greater than twice overvoltage while maintaining a desired terminal voltage, this solution requires a relatively large amount of signal monitoring and comparing to determine which PWM pulses are likely to generate greater than twice overvoltage. For this reason, it may be difficult to implement this solution using the simple microprocessors which are provided in many motor controllers.
Therefore, it would be advantageous to have a method and apparatus that could eliminate greater than twice overvoltage without distorting the fundamental components of motor terminal voltages and which is relatively simple to implement.